Apparatus and method for block interleaving in mobile communication system

ABSTRACT

A method and apparatus for block interleaving that eliminates the step of intermediary buffering. The method includes: (a) calculating a memory address at which first output data, of which number is equal to the number of rows of a first encoder is stored, (b) storing the first output data at the calculated memory address of a circular buffer, (c) storing second output data at an address which is incremented by a specific constant value from the calculated memory address of the circular buffer, and (d) storing (n+1) th  output data at an address which is incremented by n from the calculated memory address of the circular buffer.

CLAIM OF PRIORITY

This application claims the benefit under 35 U.S.C. § 119(a) from aKorean patent application filed in the Korean Intellectual PropertyOffice on Sep. 20, 2007 and assigned Serial No. 2007-95628, the entiredisclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to techniques for improving/reducing thebuffering occurring in a block interleaving system. More particularly,the present invention relates to an apparatus and method for blockinterleaving in a Long Term Evolution (LTE) communication system.

2. Description of the Related Art

Block interleaving is a technique of data transmission whereby datasequences are changed into a specific pattern (as opposed to continuoustransmission of the data sequences), in order to reduce occurrence ofburst errors (i.e., continuously generated errors).

FIG. 1 is a block diagram illustrating a structure of a conventionalsub-block interleaving method.

Referring now to FIG. 1, in the conventional method, before aread-address controller 130 interleaves outputs of a turbo encoder 110,the encoder output values are stored in a plurality of buffers 120, 125,and 127.

The read-address controller 130 functions to interleave outputs of theplurality of buffers 120, 125, and 127 and then stores the interleavedoutputs in circular buffers 140 and 145.

When using the conventional method as shown in FIG. 1, there aredisadvantages in that the buffers 120, 125, and 127 are required tostore the encoder output values.

In addition, since the encoder output values are stored in the buffers120, 125, and 127 and then interleaving is performed according to theread address controller, there is an additional problem of a increasedtime delay.

SUMMARY OF THE INVENTION

Accordingly, an exemplary aspect of the present invention is to providean apparatus and method for block interleaving in a mobile communicationsystem.

Another exemplary aspect of the present invention is to provide anapparatus and method for performing block interleaving without anintermediary buffer in a mobile communication system.

Another exemplary aspect of the present invention is to provide anapparatus and method for performing block interleaving without theinherent delay resulting from the use of an intermediary buffer in amobile communication system.

In accordance with an exemplary embodiment of the present invention, amethod for block interleaving includes: (a) calculating a memory addressat which first output data, of which number is equal to the number ofrows of a first encoder, is stored; (b) storing the first output data atthe calculated memory address of a circular buffer; (c) storing secondoutput data at an address which is incremented by a specific constantvalue from the calculated memory address of the circular buffer; and (d)storing (n+1)^(th) output data at an address which is incremented by nfrom the calculated memory address of the circular buffer.

In accordance with another exemplary embodiment of the presentinvention, an apparatus for block interleaving includes: an addresscontroller for calculating a memory address at which first output data,of which number is equal to the number of rows of a first encoder isstored, for storing the first output data at the calculated memoryaddress of a circular buffer, and for storing second output data at anaddress which is incremented by a specific constant value from thecalculated memory address of the circular buffer, and for storing(n+1)^(th) output data at an address which is incremented by n from thecalculated memory address of the circular buffer.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other exemplary aspects, features and advantages ofcertain exemplary embodiments of the present invention will be moreapparent from the following detailed description taken in conjunctionwith the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a structure of a conventionalsub-block interleaving method;

FIG. 2 is a flowchart illustrating a process of creating a tableconsidering pruning according to an exemplary embodiment of the presentinvention;

FIG. 3 is a flowchart illustrating a process of operating sub-blockinterleaving according to an exemplary embodiment of the presentinvention; and

FIG. 4 is a block diagram for sub-block interleaving according to anexemplary embodiment of the present invention.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be described belowwith reference to the accompanying drawings. For the purposes of clarityand simplicity, well-known functions or constructions may not bedescribed in detail as they would obscure appreciation of the presentinvention by a person of ordinary skill in the art with unnecessarydetail.

Hereinafter, an apparatus and method for block interleaving in a mobilecommunication system will be described in conjunction with FIGS. 2, 3and 4. In a brief overview, it will be assumed that a 32-bit column isused for interleaving in the present invention.

According to one exemplary aspect of the present invention, among allinputs, only an address of first unit data (i.e., values filled in afirst row of a block interleaver) output from an encoder is calculatedand stored in a circular buffer.

Second unit data is stored in the circular buffer according to anaddress which is incremented by +1 from the address of first unit data.That is, subsequent output addresses are recursively obtained.

Accordingly, without having to perform complex calculations to obtainall address values, subsequent address values can be easily obtainedafter calculating the address of the first unit data to be stored in thecircular buffer.

The encoder of the present invention may comprise, for example, a turboencoder 140, an example of which is shown in FIG. 4. An output format ofthe turbo encoder is predetermined, and as a result, pruning is alsodetermined.

In case of 3rd Generation Partnership Project Long Time Evolution (3GPPLTE), if a column length of the output format is 32 bits, four types ofpruning are determined. The four types of pruning are created and storedin the format of a table according to the procedure to be describedbelow. Values to be used are loaded from the table.

Now referring to FIG. 2, which is a flowchart illustrating a process ofcreating a table considering pruning according to an exemplaryembodiment of the present invention, inputs of the process are inputnumbers from 0 to 31 included in unit data. N denotes a pruning number(indicating any one of four types of pruning). In addition, an output ofthe process is the number of shifts.

First, at step 210, it is determined whether an input value is 0.

If the input value is 0, then at step 212, an output value is determinedto 0, and the output value is returned in step 245.

Otherwise, if the input value is not 0, at step 215, a local variable iis determined to 0. Thereafter, if a value of Bit Reverse Ordering (BRO)(i) is less than N in step 220, the output value is incremented by 1 instep 225. The BRO( ) denotes a 5-bit reverse ordering number dependingon the input value. For example, since a hexadecimal format of 5 is‘00101’, the result of BRO [5] is ‘10100’ (=20), that is, BRO [5]=20.

If a value of BRO (output) is equal to the local variable i in step 230,the output value in step 225 is returned in step 245.

Otherwise, if the value of BRO (output) is different from the locationvariable i in step 230, the local variable i is incremented by 1, andstep 220 and subsequent steps from the step of 220 are repeated.

The above procedure is repeated with respect to all input numbers from 0to 31.

A process that considers pruning is performed using the output values asshift values. After ending the procedure of FIG. 2, an address value tobe stored in the circular buffer is calculated. The address value is forfirst unit data to be interleaved and stored. The address value iscalculated according to Equation (1) below.

Addr[i]=BRO[i%32]*N_row−Pruning[i%32]  Equation (1)

In Equation (1), i denotes an input ordering number. Addr[i] denotes anaddress to be stored. BRO[ ] denotes a 5-bit reverse ordering numberdepending on the input value. For example, since a hexadecimal format of5 is ‘00101’, the result of BRO[5] is ‘10100’ (=20), that is, BRO[5]=20.Pruning[ ] is a value obtained by calculating a pruning number in astorage region according to an input address. N_row representsceil(N/32), and is a value obtained by dividing an input size by a unitdata number (i.e., 32).

When an address of the first unit data is generated, respective encoderoutputs in subsequent unit data are generated by adding +1 to previouslycalculated 32 address values. All encoder outputs are thus processed inthis manner, and sub-block interleaved data is stored in the circularbuffer.

If it is assumed that outputs of the turbo encoder are generated byreceiving them when the address of the first unit data is generated,then the following three address types can be required. The threeaddress types can be obtained according to Equation (2) below.

for outputs of a systematic node,

Addr[i]=BRO[i%32]*N_row−Pruning[i%32]  Equation (2)

For the outputs of systematic node, Equation (2) is identical to theEquation (1).

In Equation (2), i denotes an output ordering number. Addr[i] denotes anaddress to be stored. BRO[ ] denotes a 5-bit reverse ordering numberdepending on the input value. For example, since a hexadecimal format of5 is ‘00101’, the result of BRO[5] is ‘10100’ (=20), that is, BRO[5]=20.Pruning[ ] is a value obtained by calculating a pruning number in astorage region according to an input address. N_row representsceil(N/32), and is a value obtained by dividing an input size by a unitdata number (i.e., 32).

for outputs of a parity 1 node,

Addr[i]=2*(BRO[i%32]*N_row)−Pruning[i%32]

Herein, i denotes an input ordering number. Addr[i] denotes an addressto be stored. BRO[ ] denotes a 5-bit reverse ordering number dependingon the input value. For example, since a hexadecimal format of 5 is‘00101’, the result of BRO[5] is ‘10100’ (=20), that is, BRO[5]=20.Pruning[ ] is a value obtained by calculating a pruning number in astorage region according to an input address. N_row representsceil(N/32), and is a value obtained by dividing an input size by a unitdata number (i.e., 32).

For outputs of a parity 2 node,

Addr[i]=2*(BRO[i%32]*N_row)−Pruning[i%32]

Herein, i denotes an input ordering number. Addr[i] denotes an addressto be stored. BRO[ ] denotes a 5-bit reverse ordering number dependingon the input value. For example, since a hexadecimal format of 5 is‘00101’, the result of BRO[5] is ‘10100’ (=20), that is, BRO[5]=20.Pruning[ ] is a value obtained by calculating a pruning number in astorage region according to an input address. N_row representsceil(N/32), and is a value obtained by dividing an input size by a unitdata number (i.e., 32).

An (n+1) address for an output of each of the parity 1 node and theparity 2 node is obtained by adding 2 to the calculated addressed storedin the storage buffer.

According to the address calculated according to the first unit data, anoutput of the turbo encoder is stored in the circular buffer.

Subsequent unit data is stored in the circular buffer according toaddresses which are incremented by +1 or +2 from 32 first addresses.That is, subsequent output addresses are recursively obtained.

FIG. 3 is a flowchart illustrating a process of operating sub-blockinterleaving according to an exemplary embodiment of the presentinvention.

Referring now to FIG. 3, a table is created according to the procedureof FIG. 2 by considering a unit data number and pruning (step 310). Thisstep is performed only one time.

By using an address value calculated using Equation (2) above, an outputof a turbo encoder is stored in a circular buffer (step 320). In thisparticular case, 32 address values are first calculated.

By using an address value which is incremented by +1 from the addressvalue obtained in step 320, the output of the turbo encoder is stored inthe circular buffer in step 330 (referred to as a first process). Thefirst process is repeated until outputting of the turbo encoder isfinished (step 340).

FIG. 4 is a block diagram for sub-block interleaving according to anexemplary embodiment of the present invention.

Referring now to FIG. 4, values output from a Systematic (S) node, aParity 1 (P1) node, and a Parity 2 (P2) node of a turbo encoder 410 areblock-interleaved by an address controller 420, and then are stored incircular buffers 440 and 445.

According to this particularly exemplary embodiment in FIG. 4, a valueoutput from the S node of the turbo encoder 410 is stored in thecircular buffer 440. Values output from the P1 and P2 nodes of the turboencoder 410 are alternately stored in the circular buffer 450. Anaddress, at which the output value of the P1 node is stored, is obtainedby multiplying 2 by an address at which the output value of the S node.An address, at which the output value of the P2 node is stored, isobtained by adding 1 to an address at which the output value of the P1node is stored.

The address controller 420 calculates 32 address values of first unitdata (i.e., values output from the turbo encoder and filled in a firstrow of a block interleaver) by using a table considering pruning. Theaddress values are incremented by +1 to obtain subsequent addressvalues. The obtained address values are stored in the circular buffers440 and 445.

According to exemplary embodiments of the present invention, a hardwarestructure can be simplified by eliminating an intermediary buffer. Inaddition, a time delay can be reduced by omitting operations thatrequire the use of the intermediary buffer.

While the present invention has been shown and described with referenceto certain exemplary embodiments thereof in the description, it will beunderstood by those skilled in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the appended claims.

1. A method for block interleaving without an intermediary buffer,comprising: (a) calculating a memory address of a circular buffer atwhich a first output data, of which number is equal to a number of rowsof a first encoder, is to be stored; (b) storing the first output dataat the calculated memory address from step (a) of the circular buffer;(c) storing a second output data at an address which comprises thecalculated memory address of the circular buffer being changed by aspecific constant value; and (d) storing (n+1)^(th) output data at anaddress which is incremented by n from the calculated memory address ofthe circular buffer.
 2. The method of claim 1, wherein the second outputdata address comprises is incremented by the specific constant value. 3.The method of claim 1, further comprising, before the calculating of thememory address in step (a), creating a table for determining the firstoutput data number and for considering pruning of the number.
 4. Themethod of claim 3, wherein the creating of the table comprises: (i)determining whether an input value is 0; if the input value is 0,determining an output value to 0 and returning the output value; if theinput value is not 0, determining a local variable i to 0; after thedetermining of the local variable i to 0, if a value of outputpermutation(i) is less than N, incrementing the output value by 1; afterthe incrementing of the output value by 1, if the value of outputpermutation(output) is equal to the local variable i, returning theoutput value; if the value of output permutation(output) is not equal tothe local variable i, incrementing the local variable i by 1, return tothe step of determining whether the value of output permutation(output)is less than N; and (ii) repeating the creating of the table withrespect to all input numbers so that pruning is considered using outputvalues as shift values, wherein the output permutation(i) denotes a5-bit reverse ordering number, for example, when using BRO( ), theoutput permutation(i) is a reverse ordering number (e.g., since ahexadecimal format of 5 is ‘00101’, the result of BRO[5] is ‘10100’(=20), that is, BRO[5]=20), wherein inputs of the calculation processare input numbers 0 to 31 included in unit data, wherein N denotes apruning number (indicating any one of four types of pruning), andwherein an output of the calculation process is the number of shifts. 5.The method of claim 1, wherein the calculated memory address isexpressed by:Addr[i]=BRO[i%32]*N_row−Pruning[i%32], where i denotes an input orderingnumber, Addr[i] denotes an address to be stored, BRO[ ] denotes a 5-bitreverse ordering number depending on an input value, Pruning[ ] is avalue obtained by calculating a pruning number in a storage regionaccording to an input address, and N_row is a value obtained by dividingan input size by a unit data number.
 6. The method of claim 1, wherein,if the first encoder comprises a turbo encoder, the calculated memoryaddress for an output of a systematic node is expressed by:Addr[i]=BRO[i%32]*N_row−Pruning[i%32], where i denotes an input orderingnumber, Addr[i] denotes an address to be stored, BRO[ ] denotes a 5-bitreverse ordering number depending on the input value, Pruning[ ] is avalue obtained by calculating a pruning number in a storage regionaccording to an input address, and N_row is a value obtained by dividingan input size by a unit data number.
 7. The method of claim 1, whereinthe first encoder comprises a turbo encoder.
 8. The method of claim 1,wherein, if the first encoder comprises a turbo encoder, the calculatedmemory address for an output of a parity 1 node is expressed by:Addr[i]=2*(BRO[i%32]*N_row)−Pruning[i%32], where i denotes an inputordering number, Addr[i] denotes an address to be stored, BRO[ ] denotesa 5-bit reverse ordering number depending on an input value, Pruning[ ]is a value obtained by calculating a pruning number in a storage regionaccording to an input address, and N_row is a value obtained by dividingan input size by a unit data number.
 9. The method of claim 1, wherein,if the first encoder comprises a turbo encoder, the calculated memoryaddress for an output of a parity 2 node is expressed by:Addr[i]=2*(BRO[i%32]*N_row)−Pruning[i%32] where i denotes an inputordering number, Addr[i] denotes an address to be stored, BRO[ ] denotesa 5-bit reverse ordering number depending on the input value, that is,BRO[5]=20), Pruning[ ] is a value obtained by calculating a pruningnumber in a storage region according to an input address, and N_row is avalue obtained by dividing an input size by a unit data number.
 10. Anapparatus for block interleaving without an intermediary buffer,comprising: a first encoder for outputting encoded data values for blockinterleaving; a circular buffer for storing the values output from thefirst encoder; and an address controller for block interleaving and for(i) calculating a memory address of the circular buffer at which a firstoutput encoded data value is stored, of which number is equal to anumber of rows of the first encoder, and (ii) for storing the firstoutput data at the calculated memory address of the circular buffer, and(iii) for storing second output data at an address which is incrementedby a specific constant value from the calculated memory address of thecircular buffer, and (iv) for storing (n+1)^(th) output data at anaddress which is incremented by n from the calculated memory address ofthe circular buffer.
 11. The apparatus of claim 10, wherein, before thecalculating of the memory address, the address controller includes tablecreation means for considering the first output data number and pruning.12. The apparatus of claim 11, wherein the address controller furtherincludes means for: determining whether an input value is 0, if theinput value is 0, determining an output value to 0 and returning theoutput value, if the input value is not 0, determining a local variablei to 0, after the determining of the local variable i to 0, if a valueof output permutation(i) is less than N, incrementing the output valueby 1, after the incrementing of the output value by 1, if the value ofoutput permutation(output) is equal to the local variable i, returningthe output value, if the value of output permutation(output) is notequal to the local variable i, incrementing the local variable i by 1,return to the step of determining whether the value of outputpermutation(output) is less than N, and repeating the creating of thetable with respect to all input numbers so that pruning is consideredusing output values as shift values, wherein the output permutation(i)denotes a 5-bit reverse ordering number, for example, when using BRO( ),the output permutation(i) comprises a reverse ordering number, whereininputs of the calculation process comprise input numbers 0 to 31included in unit data, wherein N denotes a pruning number indicating atype of pruning, and wherein an output of the calculation processcomprises the number of shifts.
 13. The apparatus of claim 10, whereinthe calculated memory address is expressed by:Addr[i]=BRO[i%32]*N_row−Pruning[i%32], where i denotes an input orderingnumber, Addr[i] denotes an address to be stored, BRO[ ] denotes a 5-bitreverse ordering number depending on the input value, Pruning[ ] is avalue obtained by calculating a pruning number in a storage regionaccording to an input address, and N_row is a value obtained by dividingan input size by a unit data number.
 14. The apparatus of claim 10,wherein, if the first encoder comprises a turbo encoder, the calculatedmemory address for an output of a systematic node is expressed by:Addr[i]=BRO[i%32]*N_row−Pruning[i%32], where i denotes an input orderingnumber, Addr[i] denotes an address to be stored, BRO[ ] denotes a 5-bitreverse ordering number depending on the input value, Pruning[ ] is avalue obtained by calculating a pruning number in a storage regionaccording to an input address, and N_row representing ceil is a valueobtained by dividing an input size by a unit data number.
 15. Theapparatus of claim 10, wherein, if the first encoder comprises a turboencoder, the calculated memory address for an output of a parity 1 nodeis expressed by:Addr[i]=2*(BRO[i%32]*N_row)−Pruning[i%32] where i denotes an inputordering number, Addr[i] denotes an address to be stored, BRO[ ] denotesa 5-bit reverse ordering number depending on the input value, that is,BRO[5]=20), Pruning[ ] is a value obtained by calculating a pruningnumber in a storage region according to an input address, and N_row is avalue obtained by dividing an input size by a unit data number.
 16. Theapparatus of claim 10, wherein, if the first encoder comprises a turboencoder, the calculated memory address for an output of a parity 2 nodeis expressed by:Addr[i]=2*(BRO[i%32]*N_row)−Pruning[i%32] where i denotes an inputordering number, Addr[i] denotes an address to be stored, BRO[ ] denotesa 5-bit reverse ordering number depending on the input value, Pruning[ ]is a value obtained by calculating a pruning number in a storage regionaccording to an input address, and N_row is a value obtained by dividingan input size by a unit data number.
 17. The apparatus according toclaim 10, wherein the values output from the first encoder comprisevalues output from a Systematic (S) node, a Parity 1 (P1) node, and aParity 2 (P2) are block-interleaved by the address controller forstorage are stored in the circular buffer.
 18. The apparatus accordingto claim 10, wherein the circular buffer comprises a plurality ofcircular buffers.